An integrated circuit device represented by an arithmetic processing circuit (or a processor or a central processing unit (CPU) chip) generates power supply noise when there is a sudden change in power consumption of an internal circuit. Power supply noise is generated by the amount of current flowing in power supply wiring suddenly changing due to a sudden change in power consumption of an internal circuit and power supply voltage supplied from the power supply wiring being varied. When power supply noise is generated, there is a possibility that the internal circuit supplied with the power supply voltage malfunctions. Thus, there is a demand to lower the power supply noise as much as possible.
Regarding methods of reducing power supply noise of an arithmetic processing device or an integrated circuit device, there are descriptions in the following patent documents.
Patent literature 1: Japanese Laid-open Patent Publication No. 2013-205905
Patent literature 2: Japanese Laid-open Patent Publication No. 2014-59761
Patent literature 3: Japanese National Publication of International Patent Application No. 2013-516710
Patent literature 4: Japanese Laid-open Patent Publication No. 2009-123235
Patent literature 5: Japanese Laid-open Patent Publication No. 2004-013820
Patent literature 6: Japanese Laid-open Patent Publication No. 2001-142558
High-performance processors of recent years include a plurality of cores (or CPU cores or processor cores or arithmetic processing units) and execute a plurality of instruction sequences in parallel. Further, the high-performance processors include a plurality of arithmetic circuits within the core and execute a plurality of instruction sequences in parallel. In this manner, the power consumption of processors has increased, along with an increase in the number of cores within the processors and an increase in the number of arithmetic circuits within the cores.
In order to reduce the power consumption of such processors described above, each internal circuit represented by a register file, a random access memory (RAM), or an arithmetic circuit within the processors includes a clock gate circuit. The clock gate circuit supplies a clock to an internal circuit when in operation and stops supply of a clock when stopped. By performing fine-grained power save control utilizing the clock gate circuit in this manner, transition to the power save state is performed.
When a processor including a plurality of cores utilizes the power save control mentioned earlier in which supply of a clock is stopped, and a core shifts to the instruction processing stopped state in which processing of an instruction is stopped from the instruction processing state in which the instruction is processed, supply of a clock to a circuit within the core is stopped to reduce the power consumption of the core.
However, when the number of cores that shift to the instruction processing stopped state from the instruction processing state increases due to an increase in the number of cores within the processor, or when the number of cores that return to the instruction processing state from the instruction processing stopped state increases, the degree of increase or decrease in power consumption increases, and a great power supply noise is generated. An increase in the number of cores of a high-performance processor further increases the degree of increase or decrease in power consumption, and the degree of variation in power supply voltage due to the power supply noise increases.